Manufacture process of MOS transistors typically comprises Gate-First process and Gate-Last process. A gate stack combines metal gate electrode, and gate dielectric layer of high-dielectric-constant (high-k) material which has a low Equivalent Oxide Thickness (EOT), and is widely employed at the technology node of 32 nm and beyond.
An interface oxide layer, 4 Å or so in thickness, normally occurs between a gate dielectric layer of high-k material and a semiconductor substrate by virtue of natural oxidation. And it is difficult to scale down the equivalent oxide thickness of the gate dielectric layer of the MOS transistor to 1 nm, in which high-k material is combined with a metal gate, hindering miniature tendency of a semiconductor device.
In order to scale down the equivalent oxide thickness of the gate stack, according to prior art, a sacrificial metal layer between a gate dielectric layer, which is made of high-k material, and a metal gate electrode, is provided to remove oxygen in the interface oxide layer. Material of the sacrificial metal layer is generally Ti, Ta or the like.
FIG. 1 is a schematic cross-section view of a conventional MOS transistor. As shown in FIG. 1, the conventional MOS transistor comprises a semiconductor substrate 10; an isolation structure 11 formed in the semiconductor substrate 10; a gate stack 12 formed on the semiconductor substrate 10; and a source region 13 and a drain region 14 are respectively formed on sidewalls of the gate stack 12. The isolation structure 11 comprises shallow trench isolation (STI) structure. The gate stack 12 includes a gate dielectric layer 12a, a sacrificial metal layer 12b and a gate electrode 12c, which are formed in sequence on the semiconductor substrate 10. Material of the gate dielectric layer 12a is high-k material, material of the sacrificial metal layer 12b is Ti, Ta and the like, and material of the gate electrode 12c is metal and conductive material. An interface oxide layer 10a is provided on a surface of the semiconductor substrate 10 and below the gate dielectric 12a. After annealing and other thermal processes, the sacrificial metal layer 12b absorbs and removes oxygen in the interface oxide layer 10a and the gate dielectric layer 12a, thereby lowering the equivalent oxide thickness of the gate stack of the overall MOS transistor.
However, according to the above method, the sacrificial metal layer 12b absorbs and removes the oxygen and is converted into a metal oxide serving as a dielectric material, and thus has to be regarded as part of the equivalent oxide thickness of the gate stack of the overall MOS transistor, increasing the equivalent oxide thickness. In addition, the sacrificial metal layer 12b may not be converted into a metal oxide completely. For instance, the oxygen in the interface oxide layer 10a is insufficient to convert the sacrificial metal layer 12b to an insulating metal oxide, resulting in different work function and equivalent oxide thickness of different devices, and correspondingly deteriorating uniformity of performance parameters, such as threshold voltage, of different devices. The MOS transistor will not have stress by the above method, and thus the device performance, for instance carrier mobility, can not be raised.